A typical computer system includes a number of functional units coupled to a common bus. The functional units, which may include memory controllers, central processor units, or peripheral controller interfaces, communicate with one another over, and compete with one another for use of, the bus lines.
A very effective physical implementation has the functional units built on individual circuit boards ("unit boards" or simply "boards") which plug into corresponding parallel connectors ("slots") on a backplane or motherboard. The connectors maintain the unit boards in spaced parallel relationship with the signal traces on the motherboard extending perpendicularly thereto to define the bused signal lines.
While considerations of physical compactness tend to favor a motherboard with the minimum number of slots, flexibility considerations tend to favor many slots so that a system may be expanded as the user's needs grow.
At first blush, it would appear that one could achieve an ideal compromise by providing multiple enclosures, each having a motherboard with a relatively small number of slots. However, it would not suffice merely to string the motherboards together with connector cables to make a single large bus, since the increased length of the signal path would require a slower bus speed to allow the signals to propagate the entire length of the bus. Additionally, the signal quality may well be degraded if the signals were forced to propagate over a physically long bus.
Prior art approaches have faced these problems by treating each enclosure as a separate subsystem, and providing a communication links between enclosures. Such approaches typically require special protocols for communicating between enclosures.
A further problem arises with arbitrating competing requests for the bus. A single enclosure system usually uses a synchronous bus arbitration scheme which might, for example, operate as follows. The unit boards, in addition to making parallel connection to the bus lines on the motherboards, are serially connected in a physical daisy chain manner. Priorities are assigned strictly on the basis of the boards' relative positions in the enclosure, with any given board having a higher priority than all the boards downstream of it and a lower priority than all the boards upstream of it.
A board wishing to put data on the bus asserts a bus request signal on a dedicated bus line and asserts a disable signal on the daisy chain line to disable all the boards downstream. On the next clock edge, if the requesting board has not been disabled from above, it puts its data on the bus. Depending on the particular implementation, the board may have undisputed use of the bus for a limited number of cycles. After this number of cycles has elapsed, the board can retain control of the bus only if it has not been disabled from above (upstream). In any event, after the board has finished with the bus, it enables the daisy chain line so that the boards downstream can compete for bus cycles. The system is readily expanded to allow multiple levels of priority by providing corresponding multiple request and daisy chain lines. A requesting board, before taking the bus, would then also have to check whether a higher level of request was being asserted.
While there is no conceptual problem in extending the above-outlined synchronous arbitration regime to a multi-enclosure system, practical considerations may render the regime unsuitable. For example, it is often necessary to make the frequency of the clock dependent on the number of enclosures in order to account for propagation delays.
Therefore, despite dramatic advances in the design and implementation of small computers, it has proven very difficult to achieve compactness and a high degree of expandability without degrading overall system performance.